In a data processing system, it is common practice to interconnect several data processing units by a common bus so that they can exchange data. The bus accesses are managed by an arbitrating device which receives the access requests to the bus from the units and grants the use of the bus to a selected unit.
In synchronous data processing systems, the transmission of data bits from a source unit to a target unit, as well as the reception of data bits by the target unit and the processing of data within the units, is controlled by a clock signal which is distributed to each unit from a central clock device.
Up to now, in such synchronous systems there was no need for synchronization circuits, since each unit operated under control of the same clock signal. But as the frequency of the clock signal is increased to improve the performance of the system, the transmission delay of the data bits between two units versus the clock signal period cannot be neglected.
For example, if the units are made with logic circuitry implemented in CMOS technology, the transmission delays are equal to about 35 nanoseconds which cannot be neglected when the period of the clock signal is 40 nanoseconds.
Generally, the problem which results from the transmission delay is solved by adding to the bus lines normally used for exchanging the data at least one clock line, for transmitting a synchronization clock signal (also called STROBE signal) which is used by the receiving unit to sample the received data.
Using this synchronization clock which accompanies the data signal solves the problem which results from the transmission delay of the data bits on the bus linking the units, nevertheless the data bits sampled by the receiving unit are not in phase with the internal clock signal received by the unit from the central clock device.
U.S. Pat. No. 4,611,279 describes a circuit to be used in an asynchronous microcomputer system wherein the direct memory access controller of the memory is not synchronized to the clock signal of the microprocessor. Instead of changing the clock signal of the microprocessor to accommodate the worst case conditions of the memory accesses, the clock of the direct memory access controller is only changed when the worst case conditions occur, thus to prevent data loss. This circuit does not solve the problem of resynchronizing the received data bits with a clock signal in a synchronous data processing system.